Digital Circuits Tutorial
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Conversion of Flip-Flops
Digital Circuits - Conversion of Fpp-Flops
In previous chapter, we discussed the four fpp-flops, namely SR fpp-flop, D fpp-flop, JK fpp-flop & T fpp-flop. We can convert one fpp-flop into the remaining three fpp-flops by including some additional logic. So, there will be total of twelve fpp-flop conversions.
Follow these steps for converting one fpp-flop to the other.
Consider the characteristic table of desired fpp-flop.
Fill the excitation values (inputs) of given fpp-flop for each combination of present state and next state. The excitation table for all fpp-flops is shown below.
| Present State | Next State | SR fpp-flop inputs | D fpp-flop input | JK fpp-flop inputs | T fpp-flop input | ||
|---|---|---|---|---|---|---|---|
| Q(t) | Q(t+1) | S | R | D | J | K | T |
| 0 | 0 | 0 | x | 0 | 0 | x | 0 |
| 0 | 1 | 1 | 0 | 1 | 1 | x | 1 |
| 1 | 0 | 0 | 1 | 0 | x | 1 | 1 |
| 1 | 1 | x | 0 | 1 | x | 0 | 0 |
Get the simppfied expressions for each excitation input. If necessary, use Kmaps for simppfying.
Draw the circuit diagram of desired fpp-flop according to the simppfied expressions using given fpp-flop and necessary logic gates.
Now, let us convert few fpp-flops into other. Follow the same process for remaining fppflop conversions.
SR Fpp-Flop to other Fpp-Flop Conversions
Following are the three possible conversions of SR fpp-flop to other fpp-flops.
SR fpp-flop to D fpp-flop
SR fpp-flop to JK fpp-flop
SR fpp-flop to T fpp-flop
SR fpp-flop to D fpp-flop conversion
Here, the given fpp-flop is SR fpp-flop and the desired fpp-flop is D fpp-flop. Therefore, consider the following characteristic table of D fpp-flop.
| D fpp-flop input | Present State | Next State |
|---|---|---|
| D | Q(t) | Q(t + 1) |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
We know that SR fpp-flop has two inputs S & R. So, write down the excitation values of SR fpp-flop for each combination of present state and next state values. The following table shows the characteristic table of D fpp-flop along with the excitation inputs of SR fpp-flop.
| D fpp-flop input | Present State | Next State | SR fpp-flop inputs | |
|---|---|---|---|---|
| D | Q(t) | Q(t + 1) | S | R |
| 0 | 0 | 0 | 0 | x |
| 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | x | 0 |
From the above table, we can write the Boolean functions for each input as below.
$$S=m_{2}+d_{3}$$
$$R=m_{1}+d_{0}$$
We can use 2 variable K-Maps for getting simppfied expressions for these inputs. The k-Maps for S & R are shown below.
So, we got S = D & R = D after simppfying. The circuit diagram of D fpp-flop is shown in the following figure.
This circuit consists of SR fpp-flop and an inverter. This inverter produces an output, which is complement of input, D. So, the overall circuit has single input, D and two outputs Q(t) & Q(t) . Hence, it is a D fpp-flop. Similarly, you can do other two conversions.
D Fpp-Flop to other Fpp-Flop Conversions
Following are the three possible conversions of D fpp-flop to other fpp-flops.
D fpp-flop to T fpp-flop
D fpp-flop to SR fpp-flop
D fpp-flop to JK fpp-flop
D fpp-flop to T fpp-flop conversion
Here, the given fpp-flop is D fpp-flop and the desired fpp-flop is T fpp-flop. Therefore, consider the following characteristic table of T fpp-flop.
| T fpp-flop input | Present State | Next State |
|---|---|---|
| T | Q(t) | Q(t + 1) |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
We know that D fpp-flop has single input D. So, write down the excitation values of D fpp-flop for each combination of present state and next state values. The following table shows the characteristic table of T fpp-flop along with the excitation input of D fpp-flop.
| T fpp-flop input | Present State | Next State | D fpp-flop input |
|---|---|---|---|
| T | Q(t) | Q(t + 1) | D |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
From the above table, we can directly write the Boolean function of D as below.
$$D=Toplus Qleft ( t ight )$$
So, we require a two input Exclusive-OR gate along with D fpp-flop. The circuit diagram of T fpp-flop is shown in the following figure.
This circuit consists of D fpp-flop and an Exclusive-OR gate. This Exclusive-OR gate produces an output, which is Ex-OR of T and Q(t). So, the overall circuit has single input, T and two outputs Q(t) & Q(t)’. Hence, it is a T fpp-flop. Similarly, you can do other two conversions.
JK Fpp-Flop to other Fpp-Flop Conversions
Following are the three possible conversions of JK fpp-flop to other fpp-flops.
JK fpp-flop to T fpp-flop
JK fpp-flop to D fpp-flop
JK fpp-flop to SR fpp-flop
JK fpp-flop to T fpp-flop conversion
Here, the given fpp-flop is JK fpp-flop and the desired fpp-flop is T fpp-flop. Therefore, consider the following characteristic table of T fpp-flop.
| T fpp-flop input | Present State | Next State |
|---|---|---|
| T | Q(t) | Q(t + 1) |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
We know that JK fpp-flop has two inputs J & K. So, write down the excitation values of JK fpp-flop for each combination of present state and next state values. The following table shows the characteristic table of T fpp-flop along with the excitation inputs of JK fppflop.
| T fpp-flop input | Present State | Next State | JK fpp-flop inputs | |
|---|---|---|---|---|
| T | Q(t) | Q(t + 1) | J | K |
| 0 | 0 | 0 | 0 | x |
| 0 | 1 | 1 | x | 0 |
| 1 | 0 | 1 | 1 | x |
| 1 | 1 | 0 | x | 1 |
From the above table, we can write the Boolean functions for each input as below.
$$J=m_{2}+d_{1}+d_{3}$$
$$K=m_{3}+d_{0}+d_{2}$$
We can use 2 variable K-Maps for getting simppfied expressions for these two inputs. The k-Maps for J & K are shown below.
So, we got, J = T & K = T after simppfying. The circuit diagram of T fpp-flop is shown in the following figure.
This circuit consists of JK fpp-flop only. It doesn’t require any other gates. Just connect the same input T to both J & K. So, the overall circuit has single input, T and two outputs Q(t) & Q(t)’. Hence, it is a T fpp-flop. Similarly, you can do other two conversions.
T Fpp-Flop to other Fpp-Flop Conversions
Following are the three possible conversions of T fpp-flop to other fpp-flops.
T fpp-flop to D fpp-flop
T fpp-flop to SR fpp-flop
T fpp-flop to JK fpp-flop
T fpp-flop to D fpp-flop conversion
Here, the given fpp-flop is T fpp-flop and the desired fpp-flop is D fpp-flop. Therefore, consider the characteristic table of D fpp-flop and write down the excitation values of T fpp-flop for each combination of present state and next state values. The following table shows the characteristic table of D fpp-flop along with the excitation input of T fpp-flop.
| D fpp-flop input | Present State | Next State | T fpp-flop input | |
|---|---|---|---|---|
| D | Q(t) | Q(t + 1) | T | |
| 0 | 0 | 0 | 0 | |
| 0 | 1 | 0 | 1 | |
| 1 | 0 | 1 | 1 | |
| 1 | 1 | 1 | 0 | |
From the above table, we can directly write the Boolean function of T as below.
$$T=Doplus Qleft ( t ight )$$
So, we require a two input Exclusive-OR gate along with T fpp-flop. The circuit diagram of D fpp-flop is shown in the following figure.
This circuit consists of T fpp-flop and an Exclusive-OR gate. This Exclusive-OR gate produces an output, which is Ex-OR of D and Q(t). So, the overall circuit has single input, D and two outputs Q(t) & Q(t)’. Hence, it is a D fpp-flop. Similarly, you can do other two conversions.
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