Digital Circuits Tutorial
Digital Circuits Resources
Selected Reading
- Algorithmic State Machine Charts
- Finite State Machines
- Counters
- Application of Shift Registers
- Shift Registers
- Conversion of Flip-Flops
- Flip-Flops
- Latches
- Sequential Circuits
- Threshold Logic
- Programmable Logic Devices
- De-Multiplexers
- Multiplexers
- Encoders
- Decoders
- Arithmetic Circuits
- Combinational Circuits
- Two-Level Logic Realization
- Logic Gates
- Quine-McCluskey Tabular Method
- K-Map Method
- Canonical and Standard Forms
- Boolean Algebra
- Error Detection & Correction Codes
- Codes
- Signed Binary Arithmetic
- Binary Numbers Representation
- Base Conversions
- Number Systems
- Home
Digital Circuits Resources
Selected Reading
- Who is Who
- Computer Glossary
- HR Interview Questions
- Effective Resume Writing
- Questions and Answers
- UPSC IAS Exams Notes
De-Multiplexers
Digital Circuits - De-Multiplexers
De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It has single input, ‘n’ selection pnes and maximum of 2n outputs. The input will be connected to one of these outputs based on the values of selection pnes.
Since there are ‘n’ selection pnes, there will be 2n possible combinations of zeros and ones. So, each combination can select only one output. De-Multiplexer is also called as De-Mux.
1x4 De-Multiplexer
1x4 De-Multiplexer has one input I, two selection pnes, s1 & s0 and four outputs Y3, Y2, Y1 &Y0. The block diagram of 1x4 De-Multiplexer is shown in the following figure.
The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values of selection pnes s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.
| Selection Inputs | Outputs | ||||
|---|---|---|---|---|---|
| S1 | S0 | Y3 | Y2 | Y1 | Y0 |
| 0 | 0 | 0 | 0 | 0 | I |
| 0 | 1 | 0 | 0 | I | 0 |
| 1 | 0 | 0 | I | 0 | 0 |
| 1 | 1 | I | 0 | 0 | 0 |
From the above Truth table, we can directly write the Boolean functions for each output as
$$Y_{3}=s_{1}s_{0}I$$
$$Y_{2}=s_{1}{s_{0}} I$$
$$Y_{1}={s_{1}} s_{0}I$$
$$Y_{0}={s_1} {s_{0}} I$$
We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit diagram of 1x4 De-Multiplexer is shown in the following figure.
We can easily understand the operation of the above circuit. Similarly, you can implement 1x8 De-Multiplexer and 1x16 De-Multiplexer by following the same procedure.
Implementation of Higher-order De-Multiplexers
Now, let us implement the following two higher-order De-Multiplexers using lower-order De-Multiplexers.
1x8 De-Multiplexer
1x16 De-Multiplexer
1x8 De-Multiplexer
In this section, let us implement 1x8 De-Multiplexer using 1x4 De-Multiplexers and 1x2 De-Multiplexer. We know that 1x4 De-Multiplexer has single input, two selection pnes and four outputs. Whereas, 1x8 De-Multiplexer has single input, three selection pnes and eight outputs.
So, we require two 1x4 De-Multiplexers in second stage in order to get the final eight outputs. Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer in first stage so that the outputs of first stage will be the inputs of second stage. Input of this 1x2 De-Multiplexer will be the overall input of 1x8 De-Multiplexer.
Let the 1x8 De-Multiplexer has one input I, three selection pnes s2, s1 & s0 and outputs Y7 to Y0. The Truth table of 1x8 De-Multiplexer is shown below.
| Selection Inputs | Outputs | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| s2 | s1 | s0 | Y7 | Y6 | Y5 | Y4 | Y3 | Y2 | Y1 | Y0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | I |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | I | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | I | 0 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | I | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | I | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 | I | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | I | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | I | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
We can implement 1x8 De-Multiplexer using lower order Multiplexers easily by considering the above Truth table. The block diagram of 1x8 De-Multiplexer is shown in the following figure.
The common selection pnes, s1 & s0 are appped to both 1x4 De-Multiplexers. The outputs of upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4 De-Multiplexer are Y3 to Y0.
The other selection pne, s2 is appped to 1x2 De-Multiplexer. If s2 is zero, then one of the four outputs of lower 1x4 De-Multiplexer will be equal to input, I based on the values of selection pnes s1 & s0. Similarly, if s2 is one, then one of the four outputs of upper 1x4 DeMultiplexer will be equal to input, I based on the values of selection pnes s1 & s0.
1x16 De-Multiplexer
In this section, let us implement 1x16 De-Multiplexer using 1x8 De-Multiplexers and 1x2 De-Multiplexer. We know that 1x8 De-Multiplexer has single input, three selection pnes and eight outputs. Whereas, 1x16 De-Multiplexer has single input, four selection pnes and sixteen outputs.
So, we require two 1x8 De-Multiplexers in second stage in order to get the final sixteen outputs. Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer in first stage so that the outputs of first stage will be the inputs of second stage. Input of this 1x2 De-Multiplexer will be the overall input of 1x16 De-Multiplexer.
Let the 1x16 De-Multiplexer has one input I, four selection pnes s3, s2, s1 & s0 and outputs Y15 to Y0. The block diagram of 1x16 De-Multiplexer using lower order Multiplexers is shown in the following figure.
The common selection pnes s2, s1 & s0 are appped to both 1x8 De-Multiplexers. The outputs of upper 1x8 De-Multiplexer are Y15 to Y8 and the outputs of lower 1x8 DeMultiplexer are Y7 to Y0.
The other selection pne, s3 is appped to 1x2 De-Multiplexer. If s3 is zero, then one of the eight outputs of lower 1x8 De-Multiplexer will be equal to input, I based on the values of selection pnes s2, s1 & s0. Similarly, if s3 is one, then one of the 8 outputs of upper 1x8 De-Multiplexer will be equal to input, I based on the values of selection pnes s2, s1 & s0.
Advertisements