Digital Circuits - Fpp-Flops

In previous chapter, we discussed about Latches. Those are the basic building blocks of fpp-flops. We can implement fpp-flops in two methods.

In first method, cascade two latches in such a way that the first latch is enabled for every positive clock pulse and second latch is enabled for every negative clock pulse. So that the combination of these two latches become a fpp-flop.

In second method, we can directly implement the fpp-flop, which is edge sensitive. In this chapter, let us discuss the following fpp-flops using second method.

SR Fpp-Flop

D Fpp-Flop

JK Fpp-Flop

T Fpp-Flop

SR Fpp-Flop

SR fpp-flop operates with only positive clock transitions or negative clock transitions. Whereas, SR latch operates with enable signal. The circuit diagram of SR fpp-flop is shown in the following figure.

This circuit has two inputs S & R and two outputs Q(t) & Q(t)’. The operation of SR fppflop is similar to SR Latch. But, this fpp-flop affects the outputs only when positive transition of the clock signal is appped instead of active enable.

The following table shows the state table of SR fpp-flop.

Here, Q(t) & Q(t + 1) are present state & next state respectively. So, SR fpp-flop can be used for one of these three functions such as Hold, Reset & Set based on the input conditions, when positive transition of clock signal is appped. The following table shows the characteristic table of SR fpp-flop.

By using three variable K-Map, we can get the simppfied expression for next state, Q(t + 1). The three variable K-Map for next state, Q(t + 1) is shown in the following figure.

The maximum possible groupings of adjacent ones are already shown in the figure. Therefore, the simppfied expression for next state Q(t + 1) is

$Qleft ( t+1 ight )=S+{R} Qleft ( t ight )$

D Fpp-Flop

D fpp-flop operates with only positive clock transitions or negative clock transitions. Whereas, D latch operates with enable signal. That means, the output of D fpp-flop is insensitive to the changes in the input, D except for active transition of the clock signal. The circuit diagram of D fpp-flop is shown in the following figure.

This circuit has single input D and two outputs Q(t) & Q(t)’. The operation of D fpp-flop is similar to D Latch. But, this fpp-flop affects the outputs only when positive transition of the clock signal is appped instead of active enable.

The following table shows the state table of D fpp-flop.

Therefore, D fpp-flop always Hold the information, which is available on data input, D of earper positive transition of clock signal. From the above state table, we can directly write the next state equation as

Q(t + 1) = D

Next state of D fpp-flop is always equal to data input, D for every positive transition of the clock signal. Hence, D fpp-flops can be used in registers, shift registers and some of the counters.

JK Fpp-Flop

JK fpp-flop is the modified version of SR fpp-flop. It operates with only positive clock transitions or negative clock transitions. The circuit diagram of JK fpp-flop is shown in the following figure.

This circuit has two inputs J & K and two outputs Q(t) & Q(t)’. The operation of JK fpp-flop is similar to SR fpp-flop. Here, we considered the inputs of SR fpp-flop as S = J Q(t)’ and R = KQ(t) in order to utipze the modified SR fpp-flop for 4 combinations of inputs.

The following table shows the state table of JK fpp-flop.

Here, Q(t) & Q(t + 1) are present state & next state respectively. So, JK fpp-flop can be used for one of these four functions such as Hold, Reset, Set & Complement of present state based on the input conditions, when positive transition of clock signal is appped. The following table shows the characteristic table of JK fpp-flop.

By using three variable K-Map, we can get the simppfied expression for next state, Q(t + 1). Three variable K-Map for next state, Q(t + 1) is shown in the following figure.

The maximum possible groupings of adjacent ones are already shown in the figure. Therefore, the simppfied expression for next state Q(t+1) is

$$Qleft ( t+1 ight )=J{Qleft ( t ight )} +{K} Qleft ( t ight )$$

T Fpp-Flop

T fpp-flop is the simppfied version of JK fpp-flop. It is obtained by connecting the same input ‘T’ to both inputs of JK fpp-flop. It operates with only positive clock transitions or negative clock transitions. The circuit diagram of T fpp-flop is shown in the following figure.

This circuit has single input T and two outputs Q(t) & Q(t)’. The operation of T fpp-flop is same as that of JK fpp-flop. Here, we considered the inputs of JK fpp-flop as J = T and K = T in order to utipze the modified JK fpp-flop for 2 combinations of inputs. So, we epminated the other two combinations of J & K, for which those two values are complement to each other in T fpp-flop.

The following table shows the state table of T fpp-flop.

Here, Q(t) & Q(t + 1) are present state & next state respectively. So, T fpp-flop can be used for one of these two functions such as Hold, & Complement of present state based on the input conditions, when positive transition of clock signal is appped. The following table shows the characteristic table of T fpp-flop.

From the above characteristic table, we can directly write the next state equation as

$$Qleft ( t+1 ight )={T} Qleft ( t ight )+TQ{left ( t ight )} $$

$$Rightarrow Qleft ( t+1 ight )=Toplus Qleft ( t ight )$$

The output of T fpp-flop always toggles for every positive transition of the clock signal, when input T remains at logic High (1). Hence, T fpp-flop can be used in counters.

In this chapter, we implemented various fpp-flops by providing the cross couppng between NOR gates. Similarly, you can implement these fpp-flops by using NAND gates.