Digital Circuits - Multiplexers

Multiplexer is a combinational circuit that has maximum of 2ⁿ data inputs, ‘n’ selection pnes and single output pne. One of these data inputs will be connected to the output based on the values of selection pnes.

Since there are ‘n’ selection pnes, there will be 2ⁿ possible combinations of zeros and ones. So, each combination will select only one data input. Multiplexer is also called as Mux.

4x1 Multiplexer

4x1 Multiplexer has four data inputs I₃, I₂, I₁ & I₀, two selection pnes s₁ & s₀ and one output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs present at these two selection pnes. Truth table of 4x1 Multiplexer is shown below.

From Truth table, we can directly write the Boolean function for output, Y as

$$Y={S_{1}} {S_{0}} I_{0}+{S_{1}} S_{0}I_{1}+S_{1}{S_{0}} I_{2}+S_{1}S_{0}I_{3}$$

We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit diagram of 4x1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can implement 8x1 Multiplexer and 16x1 multiplexer by following the same procedure.

Implementation of Higher-order Multiplexers.

Now, let us implement the following two higher-order Multiplexers using lower-order Multiplexers.

8x1 Multiplexer

16x1 Multiplexer

8x1 Multiplexer

In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection pnes and one output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection pnes and one output.

So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since, each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output.

Let the 8x1 Multiplexer has eight data inputs I₇ to I₀, three selection pnes s₂, s₁ & s0 and one output Y. The Truth table of 8x1 Multiplexer is shown below.

We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the above Truth table. The block diagram of 8x1 Multiplexer is shown in the following figure.

The same selection pnes, s₁ & s₀ are appped to both 4x1 Multiplexers. The data inputs of upper 4x1 Multiplexer are I₇ to I₄ and the data inputs of lower 4x1 Multiplexer are I₃ to I₀. Therefore, each 4x1 Multiplexer produces an output based on the values of selection pnes, s₁ & s₀.

The outputs of first stage 4x1 Multiplexers are appped as inputs of 2x1 Multiplexer that is present in second stage. The other selection pne, s₂ is appped to 2x1 Multiplexer.

If s₂ is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I₃ to I₀ based on the values of selection pnes s₁ & s₀.

If s₂ is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I₇ to I₄ based on the values of selection pnes s₁ & s₀.

Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs as one 8x1 Multiplexer.

16x1 Multiplexer

In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer. We know that 8x1 Multiplexer has 8 data inputs, 3 selection pnes and one output. Whereas, 16x1 Multiplexer has 16 data inputs, 4 selection pnes and one output.

So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since, each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output.

Let the 16x1 Multiplexer has sixteen data inputs I₁₅ to I₀, four selection pnes s₃ to s₀ and one output Y. The Truth table of 16x1 Multiplexer is shown below.

We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering the above Truth table. The block diagram of 16x1 Multiplexer is shown in the following figure.

The same selection pnes, s₂, s₁ & s₀ are appped to both 8x1 Multiplexers. The data inputs of upper 8x1 Multiplexer are I₁₅ to I₈ and the data inputs of lower 8x1 Multiplexer are I₇ to I₀. Therefore, each 8x1 Multiplexer produces an output based on the values of selection pnes, s₂, s₁ & s₀.

The outputs of first stage 8x1 Multiplexers are appped as inputs of 2x1 Multiplexer that is present in second stage. The other selection pne, s₃ is appped to 2x1 Multiplexer.

If s₃ is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is₇ to I₀ based on the values of selection pnes s₂, s₁ & s₀.

If s₃ is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I₁₅ to I₈ based on the values of selection pnes s₂, s₁ & s₀.

Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer performs as one 16x1 Multiplexer.