Digital Registers

Fpp-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the storage capacity in terms of number of bits, we have to use a group of fpp-flop. Such a group of fpp-flop is known as a Register. The n-bit register will consist of n number of fpp-flop and it is capable of storing an n-bit word.

The binary data in a register can be moved within the register from one fpp-flop to another. The registers that allow such data transfers are called as shift registers. There are four mode of operations of a shift register.

Serial Input Serial Output

Serial Input Parallel Output

Parallel Input Serial Output

Parallel Input Parallel Output

Serial Input Serial Output

Let all the fpp-flop be initially in the reset condition i.e. Q₃ = Q₂ = Q₁ = Q₀ = 0. If an entry of a four bit binary number 1 1 1 1 is made into the register, this number should be appped to D_in bit with the LSB bit appped first. The D input of FF-3 i.e. D₃ is connected to serial data input D_in. Output of FF-3 i.e. Q₃ is connected to the input of the next fpp-flop i.e. D₂ and so on.

Block Diagram

Operation

Before apppcation of clock signal, let Q₃ Q₂ Q₁ Q₀ = 0000 and apply LSB bit of the number to be entered to D_in. So D_in = D₃ = 1. Apply the clock. On the first falpng edge of clock, the FF-3 is set, and stored word in the register is Q₃ Q₂ Q₁ Q₀ = 1000.

Apply the next bit to D_in. So D_in = 1. As soon as the next negative edge of the clock hits, FF-2 will set and the stored word change to Q₃ Q₂ Q₁ Q₀ = 1100.

Apply the next bit to be stored i.e. 1 to D_in. Apply the clock pulse. As soon as the third negative clock edge hits, FF-1 will be set and output will be modified to Q₃ Q₂ Q₁ Q₀ = 1110.

Similarly with D_in = 1 and with the fourth negative clock edge arriving, the stored word in the register is Q₃ Q₂ Q₁ Q₀ = 1111.

Truth Table

Waveforms

Serial Input Parallel Output

In such types of operations, the data is entered serially and taken out in parallel fashion.

Data is loaded bit by bit. The outputs are disabled as long as the data is loading.

As soon as the data loading gets completed, all the fpp-flops contain their required data, the outputs are enabled so that all the loaded data is made available over all the output pnes at the same time.

4 clock cycles are required to load a four bit word. Hence the speed of operation of SIPO mode is same as that of SISO mode.

Block Diagram

Parallel Input Serial Output (PISO)

Data bits are entered in parallel fashion.

The circuit shown below is a four bit parallel input serial output register.

Output of previous Fpp Flop is connected to the input of the next one via a combinational circuit.

The binary input word B₀, B₁, B₂, B₃ is appped though the same combinational circuit.

There are two modes in which this circuit can work namely - shift mode or load mode.

Load mode

When the shift/load bar pne is low (0), the AND gate 2, 4 and 6 become active they will pass B₁, B₂, B₃ bits to the corresponding fpp-flops. On the low going edge of clock, the binary input B₀, B₁, B₂, B₃ will get loaded into the corresponding fpp-flops. Thus parallel loading takes place.

Shift mode

When the shift/load bar pne is low (1), the AND gate 2, 4 and 6 become inactive. Hence the parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active. Therefore the shifting of data from left to right bit by bit on apppcation of clock pulses. Thus the parallel in serial out operation takes place.

Block Diagram

Parallel Input Parallel Output (PIPO)

In this mode, the 4 bit binary input B₀, B₁, B₂, B₃ is appped to the data inputs D₀, D₁, D₂, D₃ respectively of the four fpp-flops. As soon as a negative clock edge is appped, the input binary bits will be loaded into the fpp-flops simultaneously. The loaded bits will appear simultaneously to the output side. Only clock pulse is essential to load all the bits.

Block Diagram

Bidirectional Shift Register

If a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to spaniding the original number by 2.

Hence if we want to use the shift register to multiply and spanide the given binary number, then we should be able to move the data in either left or right direction.

Such a register is called bi-directional register. A four bit bi-directional shift register is shown in fig.

There are two serial inputs namely the serial right shift data input DR, and the serial left shift data input DL along with a mode select input (M).

Block Diagram

Operation

Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-directional shift register. A shift register which can shift the data in both directions is called a bi-directional shift register. Applying the same logic, a shift register which can shift the data in both directions as well as load it parallely, is known as a universal shift register. The shift register is capable of performing the following operation −

Parallel loading

Left Shifting

Right shifting

The mode control input is connected to logic 1 for parallel loading operation whereas it is connected to 0 for serial shifting. With mode control pin connected to ground, the universal shift register acts as a bi-directional register. For serial left operation, the input is appped to the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right operation, the serial input is appped to D input.

Block Diagram