Class B Power Amppfier

When the collector current flows only during the positive half cycle of the input signal, the power amppfier is known as class B power amppfier.

Class B Operation

The biasing of the transistor in class B operation is in such a way that at zero signal condition, there will be no collector current. The operating point is selected to be at collector cut off voltage. So, when the signal is appped, only the positive half cycle is amppfied at the output.

The figure below shows the input and output waveforms during class B operation.

When the signal is appped, the circuit is forward biased for the positive half cycle of the input and hence the collector current flows. But during the negative half cycle of the input, the circuit is reverse biased and the collector current will be absent. Hence only the positive half cycle is amppfied at the output.

As the negative half cycle is completely absent, the signal distortion will be high. Also, when the appped signal increases, the power dissipation will be more. But when compared to class A power amppfier, the output efficiency is increased.

Well, in order to minimize the disadvantages and achieve low distortion, high efficiency and high output power, the push-pull configuration is used in this class B amppfier.

Class B Push-Pull Amppfier

Though the efficiency of class B power amppfier is higher than class A, as only one half cycle of the input is used, the distortion is high. Also, the input power is not completely utipzed. In order to compensate these problems, the push-pull configuration is introduced in class B amppfier.

Construction

The circuit of a push-pull class B power amppfier consists of two identical transistors T₁ and T₂ whose bases are connected to the secondary of the center-tapped input transformer T_r1. The emitters are shorted and the collectors are given the V_CC supply through the primary of the output transformer T_r2.

The circuit arrangement of class B push-pull amppfier, is same as that of class A push-pull amppfier except that the transistors are biased at cut off, instead of using the biasing resistors. The figure below gives the detaipng of the construction of a push-pull class B power amppfier.

The circuit operation of class B push pull amppfier is detailed below.

Operation

The circuit of class B push-pull amppfier shown in the above figure clears that both the transformers are center-tapped. When no signal is appped at the input, the transistors T₁ and T₂ are in cut off condition and hence no collector currents flow. As no current is drawn from V_CC, no power is wasted.

When input signal is given, it is appped to the input transformer T_r1 which sppts the signal into two signals that are 180^o out of phase with each other. These two signals are given to the two identical transistors T₁ and T₂. For the positive half cycle, the base of the transistor T₁ becomes positive and collector current flows. At the same time, the transistor T₂ has negative half cycle, which throws the transistor T₂ into cutoff condition and hence no collector current flows. The waveform is produced as shown in the following figure.

For the next half cycle, the transistor T₁ gets into cut off condition and the transistor T₂ gets into conduction, to contribute the output. Hence for both the cycles, each transistor conducts alternately. The output transformer T_r3 serves to join the two currents producing an almost undistorted output waveform.

Power Efficiency of Class B Push-Pull Amppfier

The current in each transistor is the average value of half sine loop.

For half sine loop, I_dc is given by

$$I_{dc} = frac{(I_C)_{max}}{pi}$$

Therefore,

$$(p_{in})_{dc} = 2 imes left [ frac{(I_C)_{max}}{pi} imes V_{CC} ight ]$$

Here factor 2 is introduced as there are two transistors in push-pull amppfier.

R.M.S. value of collector current = $(I_C)_{max}/ sqrt{2}$

R.M.S. value of output voltage = $V_{CC} / sqrt{2}$

Under ideal conditions of maximum power

Therefore,

$$(P_O)_{ac} = frac{(I_C)_{max}}{sqrt{2}} imes frac{V_{CC}}{sqrt{2}} = frac{(I_C)_{max} imes V_{CC}}{2}$$

Now overall maximum efficiency

$$eta_{overall} = frac{(P_O)_{ac}}{(P_{in})_{dc}}$$

$$= frac{(I_C)_{max} imes V_{CC}}{2} imes frac{pi}{2 (I_C)_{max} imes V_{CC}}$$

$$= frac{pi}{4} = 0.785 = 78.5\%$$

The collector efficiency would be the same.

Hence the class B push-pull amppfier improves the efficiency than the class A push-pull amppfier.

Complementary Symmetry Push-Pull Class B Amppfier

The push pull amppfier which was just discussed improves efficiency but the usage of center-tapped transformers makes the circuit bulky, heavy and costly. To make the circuit simple and to improve the efficiency, the transistors used can be complemented, as shown in the following circuit diagram.

The above circuit employs a NPN transistor and a PNP transistor connected in push pull configuration. When the input signal is appped, during the positive half cycle of the input signal, the NPN transistor conducts and the PNP transistor cuts off. During the negative half cycle, the NPN transistor cuts off and the PNP transistor conducts.

In this way, the NPN transistor amppfies during positive half cycle of the input, while PNP transistor amppfies during negative half cycle of the input. As the transistors are both complement to each other, yet act symmetrically while being connected in push pull configuration of class B, this circuit is termed as Complementary symmetry push pull class B amppfier.

Advantages

The advantages of Complementary symmetry push pull class B amppfier are as follows.

As there is no need of center tapped transformers, the weight and cost are reduced.

Equal and opposite input signal voltages are not required.

Disadvantages

The disadvantages of Complementary symmetry push pull class B amppfier are as follows.

It is difficult to get a pair of transistors (NPN and PNP) that have similar characteristics.

We require both positive and negative supply voltages.