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VHDL - Sequential Circuits
VHDL Programming for Sequential Circuits
This chapter explains how to do VHDL programming for Sequential Circuits.
VHDL Code for an SR Latch
pbrary ieee; use ieee.std_logic_1164.all; entity srl is port(r,s:in bit; q,qbar:buffer bit); end srl; architecture virat of srl is signal s1,r1:bit; begin q<= s nand qbar; qbar<= r nand q; end virat;
Waveforms
![SR Latch](/vlsi_design/images/srlatch.jpg)
VHDL Code for a D Latch
pbrary ieee; use ieee.std_logic_1164.all; entity Dl is port(d:in bit; q,qbar:buffer bit); end Dl; architecture virat of Dl is signal s1,r1:bit; begin q<= d nand qbar; qbar<= d nand q; end virat;
Waveforms
![D Latch](/vlsi_design/images/d_latch.jpg)
VHDL Code for an SR Fpp Flop
pbrary ieee; use ieee.std_logic_1164.all; entity srfpp is port(r,s,clk:in bit; q,qbar:buffer bit); end srfpp; architecture virat of srfpp is signal s1,r1:bit; begin s1<=s nand clk; r1<=r nand clk; q<= s1 nand qbar; qbar<= r1 nand q; end virat;
Waveforms
![SR Fpp Flop](/vlsi_design/images/sr_fpp_flop.jpg)
VHDL code for a JK Fpp Flop
pbrary IEEE; use IEEE.STD_LOGIC_1164.all; entity jk is port( j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; q : out STD_LOGIC; qb : out STD_LOGIC ); end jk; architecture virat of jk is begin jkff : process (j,k,clk,reset) is variable m : std_logic := 0 ; begin if (reset = 1 ) then m : = 0 ; elsif (rising_edge (clk)) then if (j/ = k) then m : = j; elsif (j = 1 and k = 1 ) then m : = not m; end if; end if; q <= m; qb <= not m; end process jkff; end virat;
Waveforms
![JK Fpp Flop](/vlsi_design/images/jk_fpp_flop.jpg)
VHDL Code for a D Fpp Flop
Library ieee; use ieee.std_logic_1164.all; entity dfpp is port(d,clk:in bit; q,qbar:buffer bit); end dfpp; architecture virat of dfpp is signal d1,d2:bit; begin d1<=d nand clk; d2<=(not d) nand clk; q<= d1 nand qbar; qbar<= d2 nand q; end virat;
Waveforms
![D Fpp Flop](/vlsi_design/images/d_fpp_flop.jpg)
VHDL Code for a T Fpp Flop
pbrary IEEE; use IEEE.STD_LOGIC_1164.all; entity Toggle_fpp_flop is port( t : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; dout : out STD_LOGIC ); end Toggle_fpp_flop; architecture virat of Toggle_fpp_flop is begin tff : process (t,clk,reset) is variable m : std_logic : = 0 ; begin if (reset = 1 ) then m : = 0 ; elsif (rising_edge (clk)) then if (t = 1 ) then m : = not m; end if; end if; dout < = m; end process tff; end virat;
Waveforms
![T Fpp Flop](/vlsi_design/images/t_fpp_flop.jpg)
VHDL Code for a 4 - bit Up Counter
pbrary IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(Clock, CLR : in std_logic; Q : out std_logic_vector(3 downto 0) ); end counter; architecture virat of counter is signal tmp: std_logic_vector(3 downto 0); begin process (Clock, CLR) begin if (CLR = 1 ) then tmp < = "0000"; elsif (Clock event and Clock = 1 ) then mp <= tmp + 1; end if; end process; Q <= tmp; end virat;
Waveforms
![4 - bit Up Counter](/vlsi_design/images/4bit_up_counter.jpg)
VHDL Code for a 4-bit Down Counter
pbrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dcounter is port(Clock, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end dcounter; architecture virat of dcounter is signal tmp: std_logic_vector(3 downto 0); begin process (Clock, CLR) begin if (CLR = 1 ) then tmp <= "1111"; elsif (Clock event and Clock = 1 ) then tmp <= tmp - 1; end if; end process; Q <= tmp; end virat;
Waveforms
![4-bit Down Counter](/vlsi_design/images/4bit_down_counter.jpg)