8085 Microprocessor
- 8085 Instruction Sets
- Addressing Modes & Interrupts
- 8085 Pin Configuration
- Microprocessor - 8085 Architecture
8086 Microprocessor
- 8086 Addressing Modes
- Microprocessor - 8086 Interrupts
- 8086 Instruction Sets
- 8086 Pin Configuration
- 8086 Functional Units
- Microprocessor - 8086 Overview
Multiprocessor Configuration
I/O Interfacing
Microcontrollers
- Microcontrollers - 8051 Interrupts
- 8051 Input Output Ports
- 8051 Pin Description
- Microcontrollers - 8051 Architecture
- Microcontrollers - Overview
Peripheral Devices
- 8253/54 - Operational Modes
- 8253 - Programmable Interval Timer
- Intel 8255A - Pin Description
- Programmable Peripheral Interface
Microprocessor Useful Resources
Selected Reading
- Who is Who
- Computer Glossary
- HR Interview Questions
- Effective Resume Writing
- Questions and Answers
- UPSC IAS Exams Notes
Multiprocessor Configuration Overview
Multiprocessor means a multiple set of processors that executes instructions simultaneously. There are three basic multiprocessor configurations.
Coprocessor configuration
Closely coupled configuration
Loosely coupled configuration
Coprocessor Configuration
A Coprocessor is a specially designed circuit on microprocessor chip which can perform the same task very quickly, which the microprocessor performs. It reduces the work load of the main processor. The coprocessor shares the same memory, IO system, bus, control logic and clock generator. The coprocessor handles speciapzed tasks pke mathematical calculations, graphical display on screen, etc.
The 8086 and 8088 can perform most of the operations but their instruction set is not able to perform complex mathematical operations, so in these cases the microprocessor requires the math coprocessor pke Intel 8087 math coprocessor, which can easily perform these operations very quickly.
Block Diagram of Coprocessor Configuration
![Coprocessor Configuration](/microprocessor/images/coprocessor_configuration.jpg)
How is the coprocessor and the processor connected?
The coprocessor and the processor is connected via TEST, RQ-/GT- and QS0 & QS1 signals.
The TEST signal is connected to BUSY pin of coprocessor and the remaining 3 pins are connected to the coprocessor’s 3 pins of the same name.
TEST signal takes care of the coprocessor’s activity, i.e. the coprocessor is busy or idle.
The RT-/GT-is used for bus arbitration.
The coprocessor uses QS0 & QS1 to track the status of the queue of the host processor.
Closely Coupled Configuration
Closely coupled configuration is similar to the coprocessor configuration, i.e. both share the same memory, I/O system bus, control logic, and control generator with the host processor. However, the coprocessor and the host processor fetches and executes their own instructions. The system bus is controlled by the coprocessor and the host processor independently.
Block Diagram of Closely Coupled Configuration
![Closely Coupled Configuration](/microprocessor/images/closely_coupled_configuration.jpg)
How is the processor and the independent processor connected?
Communication between the host and the independent processor is done through memory space.
None of the instructions are used for communication, pke WAIT, ESC, etc.
The host processor manages the memory and wakes up the independent processor by sending commands to one of its ports.
Then the independent processor accesses the memory to execute the task.
After completion of the task, it sends an acknowledgement to the host processor by using the status signal or an interrupt request.
Loosely Coupled Configuration
Loosely coupled configuration consists of the number of modules of the microprocessor based systems, which are connected through a common system bus. Each module consists of their own clock generator, memory, I/O devices and are connected through a local bus.
Block Diagram of Loosely Coupled Configuration
![Loosely Coupled Configuration](/microprocessor/images/loosely_coupled_configuration.jpg)
Advantages
Having more than one processor results in increased efficiency.
Each of the processors have their own local bus to access the local memory/I/O devices. This makes it easy to achieve parallel processing.
The system structure is flexible, i.e. the failure of one module doesn’t affect the whole system failure; faulty module can be replaced later.